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HT9480 pager controller features operating voltage: 2.2v~3.5v low power crystal oscillator control C 512, 1200, or 2400 bps data rate operation decodes ccir radio-paging code no.1 (pocsag code) 2-bit random and optional 4-bit burst error correction improved synchronization algorithm supports up to 6 independently program- mable user addresses and 6 user frames three rf power on timing control pins single crystal for all available baud rate (76.8khz crystal) battery low indication (external detector) battery fail interrupt and data ready interrupt 8k 16 program rom 416 8 data ram 35 4 lcd display 7 input lines and 10 bidirectional i/o lines 8-bit programmable timer for rtc interrupt 8-bit programmable timer/event counter and overflow interrupt 8-bit programmable tone generator with buzzer output watchdog timer halt function and wake-up feature reduce power consumption 63 powerful instructions, most instructions in one machine cycle eight-level subroutine nesting table read instruction inverted or non-inverted input signal selection for decoder input 80-pin lqfp package general description the HT9480 is a high performance pager con- troller. the built-in single cycle instructions (16-bit wide) and two-stage pipeline architec- ture of the HT9480 account for its high perform- ance. the controller contains a full function pager decoder (pocsag code) at 512, 1200, or 2400 bits per second data rate and an lcd display driver with a 35 4 dot output. 1 23th feb 98
pin assignment HT9480 2 23th feb 98
block diagram HT9480 3 23th feb 98
pin description pin no pin name i/o function 43~49 pa0~pa6 i 7-bit input ports, with pull-high resistors each bit can be configured as a wake-up input by mask option. 54~61 pb0~pb7 i/o bidirectional 8-bit input/output ports, pull-high mask option the output structures, whether tri-state or cmos, are determined by software instructions. 62~63 pc0~pc1 i/o bidirectional 2-bit input/output ports, pull-high mask option the output structures, whether tri-state or cmos, are determined by software instructions. 1, 42, 52, 64 vss negative power supply (gnd) 76 77 x1 x2 i o x1 and x2 are connected to an external crystal to form an internal low power oscillator clock. 40 41 osc1 osc2 i o osc1 and osc2 are connected to an rc network or a crystal (determined by mask option) to form the system clock oscillator. for rc operation, osc2 is the output terminal of the system clock. 53 res i schmitt trigger reset input, active low 68 baf i battery fail interrupt with debounce circuit input 50 tmr1 i schmitt trigger input for timer/event counter 2, 39, 51 67 vdd positive power supply 65 bz o buzzer non-inverting bz output the bz pin outputs high at buzzer off (by setting the value 00h of 1dh) 3~34 78~80 seg31~seg0 seg34~seg32 o lcd driver outputs for lcd panel segments 35~38 com3~com0 o outputs for lcd panel common connections 66 tsc i m c test mode input pin, active low with pull-high resistor 75 ts i decoder test mode input pin, active low with a pull-high resistor 69 bal i battery low indication input, active high without pull-high resistor 70 di i pocsag code input serial data (inverting or non-inverting as determined by spf32). cmos input without pull-high resistor 71 bs1 o pager receiver power control enable output, cmos output 72 bs2 o rf dc level adjustment pin, cmos output 73 bs3 o pll control pin, cmos output 74 fout o frequency reference output pin the fout output pin produces a 76.8khz/153.6khz signal with a 1/2 duty cycle reference frequency if a 76.8khz crystal is used. HT9480 4 23th feb 98
absolute maximum ratings* supply voltage .............................. C0.3v to 5.5v storage temperature................. C50 c to 125 c input voltage..................v ss C0.3v to v dd +0.3v operating temperature............... C25 c to 85 c *note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. d.c. characteristics (ta=25 c) symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3v application 2.2 3.0 3.5 v i dd operating current 3v no load, fsys=153.6khz 300 m a i stb1 standby current 1 3v no load, system halt (watchdog on) 200 m a i stb2 standby current 2 3v no load, system halt (watchdog off) 1 m a v il input low voltage for input port and i/o port 3v 0 1 v v ih input high voltage for input port and i/o port 3v 2.2 3 v v il1 input low voltage ( res,tmr1,bal) 3v 0 1 v v ih1 input high voltage ( res,tmr1,bal) 3v 2.2 3 v v il2 input low voltage ( baf) 3v 0 0.9 v v ih2 input high voltage ( baf) 3v 1.3 3 v i ol i/o port sink current 3v v ol =0.3v 1.7 3.4 ma i oh i/o port source current 3v v oh =2.7v C1 C1.9 ma i ol segment 0-34 output sink current 3v v ol =0.3v 20 44 m a i oh segment 0-34 output source current 3v v oh =2.7v C20 C38 m a i ol bz, sink current 3v v ol =0.3v 1 2.5 ma i oh bz, source current 3v v oh =2.7v C1 C2 ma HT9480 5 23th feb 98
symbol parameter test conditions min. typ. max. unit v dd conditions i ol pc0~pc1 sink current 3v v ol =0.3v 1.7 3.4 ma i oh pc0~pc1 source current if pull-high mask option 3v v oh =2.7v C1 C1.9 ma i ol bs1, bs2, bs3, fout sink current 3v v ol =0.3v 350 m a i oh bs1, bs2, bs3, fout source current 3v v oh =2.7v C0.9 ma r ph pull-high i/o port resistance 3v 100 200 500 k w a.c. characteristics (ta=25 c) symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (rc osc) 3v 76.8 256 1000 khz f sys2 system clock (crystal osc) 3v 76.8 256 1000 khz f subsys pager subsystem clock (crystal osc) 3v 32.768 76.8 153.6 khz f timer timer i/p frequency (tmr1) 3v 0 1000 khz t res external reset low pulse width 1 m s t int interrupt pulse width 1 m s * note: t sys =1/f sys HT9480 6 23th feb 98
execution flow system architecture execution flow the HT9480 system clock can be derived from either a crystal or an rc oscillator. it is inter- nally divided into four non-overlapping clocks denoted by p1, p2, p3, and p4. each instruction cycle consists of t1 to t4. instruction fetching and execution are pipe- lined in such a way that a fetch takes an in- struction cycle while decoding and execution take the next instruction cycle. the pipelining scheme causes each instruction to effectively execute within a cycle. if an instruction changes the content of the program counter two cycles are required to complete the instruction. program counter C pc the program counter (pc) is 13-bit wide and controls the program rom instruction se- quence execution. the contents of the pc can specify a of maximum 8192 addresses. mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 0 0000000000 0 data ready interrupt and battery fail interrupt 0 0 0000000010 0 programmable timer interrupt 0 0 0000000100 0 timer/event counter interrupt 0 0 0000000110 0 skip pc+2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12#11#10#9#8#7#6#5#4#3#2#1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter notes: *12~*0: program counter bits #12~#0: instruction code bits s12~s0: stack register bits @7~@0: pcl bits HT9480 7 23th feb 98
the pc value is incremented by one after a program memory word is accessed in order to fetch an instruction code. the pc then points to a memory word with the next instruction code. the pc loads the address corresponding to each instruction and then manipulates program transfer while executing a jump instruction, conditional skip execution, loading a pcl, a register, a subroutine call, an initial reset, an internal interrupt, an external interrupt, or re- turning from a subroutine. the conditional skip is activated by instruc- tions. once the condition is satisfied, the next instruction, fetched during the current instruc- tion execution, is discarded, and a dummy cycle is replaced to get a proper instruction. other- wise it proceeds with the following instruction. the low byte of the pc (pcl) is a readable and writable register (06h). moving data into the pcl performs a short jump. the destination is within 256 locations. if a control transfer takes place, an additional dummy cycle is required. program memory C rom the program memory (rom) is used to store the program instructions that are to be exe- cuted. it consists of data, table(s), and interrupt entries, and is organized into 8192 16 bits, which are addressed by the pc and table pointer. certain locations in the rom are reserved for specific usage: location 0000h location 0000h is reserved for program in- itialization. the program always begins exe- cution at this location each time the chip is reset. location 0004h location 0004h is reserved for the data ready interrupt and battery fail interrupt service programs. if an interrupt results from a pager decoder interrupt request or from a battery fail interrupt request, and the interrupt is enabled, and the stack is not full, the program begins execution at location 0004h. the oc- currence of a data ready interrupt or a battery fail interrupt is detected by checking the bat- tery fail interrupt bit (1eh-bit 4, bf flag) and the data ready interrupt bit (1eh-bit 7, dr flag). the interrupt should be carefully proc- essed if both interrupt bits are active. location 0008h location 0008h is reserved for the program- mable timer interrupt service program. if an interrupt results from a programmable timer interrupt request (its source is from 256hz divided by n, where the value of n ranges from 1 to 256.), and the interrupt is enabled, and the stack is not full, the program begins execution at location 0008h. location 000ch location 000ch is reserved for the timer/event counter interrupt service program. if a timer interrupt results from a timer/event counter overflow, and the interrupt is enabled, and the stack is not full, the program begins execution at location 000ch. look-up tables xx00h~xxffh the rom is composed of 32 groups (each group contains 256 continuous words) which can be used as lookCup tables. the instruc- tions tabrdc [m] (the current table) and tabrdl [m] (the last table) transfer the contents of the low-order byte to the specified data memory, and the contents of the high-or- der byte to tblh (table high-order byte reg- program memory HT9480 8 23th feb 98
ister) (08h). only the destination of the low- order byte in the table is well-defined, the other bits of the table word are all transferred to the low portion of tblh. tblh is read only while the table pointer (tblp) is a read- able/writable register (07h) used to indicate the table location. before accessing the table, the location should be placed in tblp. all of the table related instructions require 2 cycles to complete the operation. this feature is effi- cient only for the movement of the blocks, which may function as look-up tables or as a normal program memory depending upon the requirements. stack register C stack the stack register is a special memory port used to save the contents of the pc. it is divided into 8 levels. the stack register is neither part of the data nor part of the program, and is neither readable nor writable. the activated level of the stack register is indexed by the stack pointer (sp), and is neither readable nor writable. at the commencement of a subroutine call or an interrupt acknowledge, the contents of the pc is pushed onto the stack. at the end of the subrou- tine or the interrupt routine, as signaled by a return instruction (ret or reti), the content s of the pc is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt occurs, the interrupt request flag is recorded but acknowledging is inhibited until the value of the sp is decremented (by ret or reti), allowing that interrupt to be serviced. as this feature can prevent a stack overflow, the use of the structure becomes much easier. in a similar case, if the stack is full, and a call is sub- sequently executed, a stack overflow occurs and the first entry is lost (only the most recent eight return addresses are stored). data memory C ram the data memory (ram) is designed in three banks, i.e., bank 0, bank 1, and bank 27, and comprised of four functional groups, namely special function registers (of 22 8 bits; 1 4 bit; 1 2 bit in bank0), data memory (of 416 8 bits; 224 8 in bank 0; 192 8 in bank 1), lcd display mapping memory (of 35 4 bits), and decoder configuration ram mapping memory (of 21 8 bits). most of the these groups are readable/wri- table but some are read only. of the four functional groups, the special func- tion registers of bank 0 consist of an indirect addressing registers (iar0;00h, iar1;02h), memory pointer registers (mp0;01h, mp1;03h), a memory bank pointer register (bp;04h), an accumulator (acc;05h), a pro- gram counter low byte register (pcl;06h), a table pointer (tblp;07h), a table high-order part register (tblh;08h), a watchdog timer option setting register (wdts;09h), a status register (status;0ah), an interrupt control register (intc;0bh), a programmable timer counter (tmr0;0dh), a programmable timer counter control register (tmrc0;0eh), a timer/event counter (tmr1;10h), a timer/event counter control register (tmrc1;11h), an input port, two i/o ports (pa;12h, pb;14h, pc;16h), two i/o control register (pbc;15h, pcc;17h), a tone control register (1dh), a pager control reg- ister (1eh), and a pager data register (1fh). the special function registers are located from 00h to 1fh whereas the 32 global data regis- instruction(s) table location *12*11*10*9*8*7*6*5*4*3*2*1*0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111@7@6@5@4@3@2@1@0 notes: *12~*0: table location bits @7~@0: table pointer bits p12~p8: current program counter bits HT9480 9 23th feb 98
ram mapping HT9480 10 23th feb 98
ters are from 20h to 3fh, where each bank points to the same location. the other spaces, namely 0ch, 0fh, 13h, the high nibble of 16h, 17h, and 18h~1ch, are all reserved for future expansion usage; reading these locations will get an 00h value. on the other hand, the general purpose data memory, divided into three banks (bank 0, bank 1, and bank 27), is used for data, control infor- mation, and lcd display control under instruc- tion commands. the banks in the ram are all addressed from 40h to ffh, and are selected by setting the value (00h: bank 0; 01h: bank 1; 1bh: bank 27) of the bank pointer (bp;04h). the bank27 memory is used for lcd display mapping and the decoder configuration ram mapping. the spaces from 4fh to bfh and from e3h to ffh, and the high nibble part from c0h to e2h in bank 27 are all reserved for future expansion usage; reading these locations will derive 00h. the special registers, global data registers and general data memory can directly perform arithmetic, logic, increment, decrement, and ro- tate operations. each bit in the ram can be set and reset by set [m].i and clr [m].i, and can also be indirectly accessible through the memory pointer registers (mp0;01h, mp1;03h). of the special addresses, 1dh and 1fh cannot directly do all these operations, because they are not read and write accessible addresses. 1dh is a write-only address, 1fh a read-only address, but these two addresses namely, 1dh and 1fh can only perform operations by using the mov instruction. indirect addressing register iarx (iar0;00h, iar1;02h) are indirect ad- dress registers that are not physically imple- mented. any read/write operation of the iarx accesses the data memory pointed to by mpx (mp0;01h, mp1;03h). reading the indirect ad- dressing register itself will indirectly derive 00h, while writing the indirect addressing reg- ister indirectly will lead to no operations. (iar0, mp0) is indirectly addressable in bank 0, but (iar1, mp1) is available for all banks. accumulator C acc the accumulator (acc) relates to the alu opera- tions. it is also mapped to location 05h of the data memory and is capable of carrying out immediate data operations. data movement between these two data memories has to pass through the acc. arithmetic and logic unit C alu this circuit performs 8-bit arithmetic and logic operations, and provides the following functions: arithmetic operation (add, adc, sub, sbc, daa) logic operation (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz, etc.) the alu not only saves the results of data operation, but also changes the contents of the status register. status register C status the status register (0ah) is 8-bit wide. it contains a zero flag (z), a carry flag (c), an auxiliary carry flag (ac), an overflow flag (ov), a powerdown flag (pd), and a wdt time-out flag (to). the status register not only records the status information, but also controls the operation sequence. the status register, like most other registers, can be altered by instructions except for the to and pd flags. any data written into the status register will not change to or pd. it should be noted that operations related to the status reg- ister may derive different results from those intended. for example, clearing the status reg- ister clr [0ah] has no effect on the to and pd flags, and the value of the zero flag is also 1, i.e., uu0100 is the data in the register, where the value of u is an unchanged value. the z, ov, ac, and c flags generally reflect the status of the latest operations. on entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. if the con- tents of the status is important, and if the sub- routine may corrupt the status register, the programmer should take precautions to save it properly. HT9480 11 23th feb 98
labels bits function c0 c is set if the operation results in a carry out in addition or if a borrow does not take place in subtraction; otherwise c is cleared. c is also affected by a rotate through carry instructions. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or if a borrow from the high nibble into the low nibble does not take place in subtraction; otherwise ac is cleared. z2 z is set if the result of an arithmetic or a logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the high-order bit but not a carry out of the high-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared during power up, and set by a halt instruction. to 5 to is cleared during power up or by a clr wdt instruction and a halt instruction. to is set by a current timer time-out. - 6 undefined, read as 0 - 7 undefined, read as 0 status register interrupts the HT9480 provides an internal programma- ble timer interrupt, an internal data ready in- terrupt, timer/event counter interrupt, and a battery fail interrupt. the internal data ready interrupt and the battery fail interrupt employ the same jump location (04h). the interrupt control register (intc;0bh) contains interrupt control bits to set not only the enable/disable status but also the interrupt request flags. once an interrupt subroutine is serviced, the other interrupts will all be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt re- quests may occur during this interval, but only the interrupt request flag is recorded. if a cer- tain interrupt requires servicing within the service routine, the emi bit and the correspond- ing bit of the intc register may be set to permit interrupt nesting. when the stack is full, the interrupt request will not be acknowledged even if the related interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becoming full. all of these interrupts can support the wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the contents of the pc onto the stack, followed by a branch to a subroutine at the specified location in the pro- gram memory. only the contents of the pc is pushed onto the stack. if the contents of the register or of the status register (status) is altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. the data ready interrupt and battery fail inter- rupt share the same subroutine call location 04h. checking the battery fail interrupt bit ( bf;bit 4 of 1eh) and the data ready interrupt bit ( dr; bit 7 of 1eh) can determine which kind of interrupt has occurred. the value of 1eh-bit 7 dr is cleared 0 by the decoder data ready interrupt signal, and is set to 1 when the m c sets this bit high. both interrupt bits are active low. the data ready interrupt is generated by the pager decoder after a valid call is received, and is initialized by setting the data ready interrupt request flag (eif; bit 4 of intc) and the data HT9480 12 23th feb 98
ready interrupt bit ( dr; bit 7 of 1eh). once the data ready interrupt is triggered, the stack is not full, and the emi bit is set, a subroutine call to location 04h will occur. the related interrupt request flag (eif) will, however, be reset, and the emi bit cleared to disable further inter- rupts. this interrupt should be processed care- fully if the battery fail interrupt is activated as well. the battery fail interrupt, on the other hand, is triggered by a high to low transition on baf. when the battery fail interrupt is enabled, the stack is not full, and the interrupt request flag (eif; bit 4 of intc) is set, a subroutine call to location 04h will occur. the related interrupt request flag (eif) will also be reset, and the emi bit be cleared to disable other interrupts. the programmable timer interrupt is automat- ically triggered at a rate of 256hz/n (where the value of n ranges from 1 to 256), and then the interrupt request flag (t0f; bit 5 of intc) is set. when the timer interrupt is enabled, the stack is not full, and the programmable timer interrupt is activated, a subroutine call to loca- tion 08h will occur. then, the related interrupt request flag (t0f) will be reset, and the emi bit cleared to disable other interrupts. the timer/event counter interrupt is initialized by setting the timer/event counter interrupt re- quest flag (t1f; bit 6 of intc), which is nor- mally caused by a timer overflow. when the interrupt is enabled, the stack is not full, and the t1f bit is set, a subroutine call to location 0ch will occur. the related interrupt request flag (t1f) will be reset, and the emi bit cleared to disable further interrupts. during the execution of an interrupt subrou- tine, other interrupt acknowledgments are all held until the reti instruction is executed, or the emi bit and the related interrupt control bit are both set to 1 (if the stack is not full). to return from the interrupt subroutine, a ret or reti instruction may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. the interrupts are serviced between the rising edges of the two adjacent t2 clocks. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. register bit no. label function intc (0bh) 0emi controls the master (global) interrupt (1=enabled; 0=disabled) 1 eei controls the data ready and battery fail interrupts (1=enabled; 0=disabled) 2et0i controls the programmable timer interrupt (1=enabled; 0=disabled) 3et1i controls the timer/event counter interrupt (1=enabled, 0=disabled) 4eif internal data ready and battery fail interrupt request flag (1=active; 0=inactive) 5t0f internal programmable timer interrupt request flag (1=active; 0=inactive) 6t1f timer/event counter request flag (1=active; 0=inactive) 7 -- unused bit, read as 0 intc register HT9480 13 23th feb 98
no. interrupt source priority vector a data ready interrupt and battery fail interrupt 104h c programmable timer interrupt 208h d timer/event counter overflow 30ch the programmable timer interrupt request flag (t0f), timer/event counter interrupt request flag (t1f), data ready interrupt and battery fail interrupt request flag (eif), enable timer/event counter bit (et1i), enable data ready interrupt bit (eei), and enable programmable timer in- terrupt bit (et0i) make up the register intc which is located at 0bh in the data memory. the eei, et0i, et1i, and emi bits are all used to control the enable/disable status of the inter- rupts, preventing the requested interrupt from being serviced. once the interrupt request flags (t0f, t1f, and eif) are set, they will remain in the intc register until the interrupts are serv- iced or cleared by a software instruction. a call subroutine in the interrupt subrou- tine should be used. this is because interrupts often occur in an unpredictable manner or need to be immediately serviced in some applica- tions. during this time, if only one stack is left, and enabling the interrupt is not well control- led, the operation of a call subroutine in the interrupt service routine is quite likely to upset the original control sequence. oscillator configuration the system core and the pager subsystem of the HT9480 are clocked by different oscillators. the system oscillator can be either a crystal or an rc type. the subsystem low power oscillator, on the other hand, is a crystal type which is de- signed with the power on start-up function to reduce the stabilization time of the oscillator. this start-up function is enabled by pc2 which is initially set high at power on reset, and should be cleared so as to enable the low-power oscillator function. the oscillator configuration is running in the low power mode. the system oscillator can be configured as either an rc or crystal type of oscillator, deter- mined by mask option. no matter what kind of oscillator type is selected, the signal provides a system clock. the system clock may also be externally connected. the halt mode stops the system oscillator and ignores external sig- nals to conserve power. if the system oscillator is an rc type oscillator, an external resistor between osc1 and osc2 is required. the system clock is available on osc2, which can be used to synchronize exter- nal logic. an rc oscillator provides the most cost-effective solution. the frequency of oscilla- tion may vary with power, temperature, and the chip itself due to process variations. the rc oscillator is, therefore, not suitable for timing sensitive operations where an accurate oscilla- tor frequency is desired. on the other hand, if a crystal type oscillator is used, a crystal across osc1 and osc2 is re- quired to provide the feedback and phase shift for oscillation, and no other external compo- nents are required. a ceramic resonator can replace the crystal connected between osc1 and osc2 to derive a frequency reference. in this case, two external capacitors at osc1 and osc2 are required. low power oscillator HT9480 14 23th feb 98
division ratio option crystal type and time-out period ws2 ws1 ws0 division ratio 153.6khz 76.8khz 32.768khz 0 0 0 1:1 13.3ms 26.7ms 62.5ms 0 0 1 1:2 26.7ms 53.3ms 125ms 0 1 0 1:4 53.3ms 106.7ms 250ms 0 1 1 1:8 106.7ms 213.3ms 500ms 1 0 0 1:16 213.3ms 426.7ms 1000ms 1 0 1 1:32 426.7ms 853.3ms 2000ms 1 1 0 1:64 853.3ms 1706.7ms 4000ms 1 1 1 1:128 1706.7ms 3413.3ms 8000ms wdts register an external clock can also be applied to osc1. in this application, the mask option for the crystal type oscillator should be selected, and osc2 kept open. the low power crystal oscillator is designed for the pager subsystem and is used to clock the frequency divider, pager decoder, and lcd driver. when the system enters the powerdown mode the crystal oscillator for the pager subsys- tem keeps running. watchdog timer C wdt the clock source of the watchdog timer (wdt) is implemented by a subsystem clock (wdtclk from the pager subsystem which re- mains running during a system halt) or by an instruction clock (the system clock divided by 4), that is decided by mask option. the value of wdtclk can be set as 153.6khz/1024 (or 2048), 76.8khz/1024 (or 2048), or 32.768khz/1024 (or 2048), depending upon the different crystal type. the wdt is the program designed to avoid software malfunctions or sequence from jumping to an unknown location with unpre- dictable results. it can be disabled by mask option. if the wdt is disabled, all the execu- tions related to the wdt lead to no operations. if the subsystem clock is selected, it is first divided by 256 (8 stages) to get the nominal time-out period. longer time-outs can be real- ized by invoking the wdt prescaler. writing data to ws2, ws1, and ws0 (bits 2,1,0 of the wdts) can yield different time-out periods. if the values of ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128. on the other hand, if the instruction clock is applied, the wdt operates in the same manner as the case when the subsystem clock is chosen, except that in the halt state the wdt stops counting and lose its protection purpose. in this situation, the wdt logic can be restarted by external logic. the high nibble and bit 3 of the wdts is reserved for user defined flags, which can be used to indicate some specified status. the overflow of the wdt under normal opera- tion not only initializes the chip reset, but sets the status bit to. an overflow in the halt system clock oscillator HT9480 15 23th feb 98
watchdog timer mode initializes a warm reset only when the pc and sp are reset to zero. to clear the con- tents of the wdt (including the wdt pres- caler), there are three methods to be adopted namely, external reset (a low level to res), software instruction(s), and a halt instruc- tion. there are two types of software instruc- tions, clr wdt and clr wdt1/clr wdt2. but only one of these two types of in- structions can be active at a time depending on the mask option - clr wdt times selection option. if the clr wdt is selected (i.e., clrwdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clrwdr times equal two), these two instructions should be executed to clear the wdt; otherwise, the wdt may reset the chip due to a time-out. powerdown operation C halt the halt mode is initialized by the halt instruction and results in the following. the system turns off. the low power oscillator, tone generator, lcd driver, pager decoder, and wdt oscillator all keep running (if the wdt oscillator is selected). the contents of the onCchip ram and of the registers remain unchanged. the wdt and the wdt prescaler are cleared and counted again (if the wdt clock is from the wdt oscillator). all the i/o ports remain in their original status. the pd flag is set but the to flag is cleared. the system can quit the halt mode by an external reset, an interrupt, an external falling edge signal on port a, or a wdt overflow. an external reset leads to device initialization and the wdt overflow performs a warm reset. after the to and pd flags are examined, the reason for the chip reset is determined. the pd flag that is cleared on power-up is set after the halt instruction is executed. the to flag is set when the wdt time-out occurs, which causes a wake-up that resets only the pc and sp, and leaves the others in their original status. the port a wake-up and interrupt methods can be considered as a continuation of normal exe- cution. every bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stimulation, the program resumes execution of the next instruc- tion. however, if the program awakens from an interrupt, two sequences may occur. the pro- gram will resume execution at the next instruc- tion if the related interrupt(s) is (are) disabled or the interrupt(s) is (are) enabled but the stack is full. a regular interrupt response, on the other hand, may take place if the interrupt is enabled and the stack is not full. if the wake-up event(s) occurs and the wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution is delayed by one or more cycles. on the other hand, if the wake- up brings about the following instruction execu- tion, the actual interrupt subroutine is executed immediately after the dummy period is completed. to minimize power consumption, the i/o pins should all be carefully managed before entering the halt status. HT9480 16 23th feb 98
reset there are five ways in which a reset can occur: power on reset (por) res reset during normal operation res reset during halt wdt time-out reset during normal operation wdt time-out reset during halt the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm reset that just resets the pc and sp, leaving the other circuits to keep their state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset condi- tions are met. by examining the pd and to flags, the program can distinguish between dif- ferent chip resets. to pd reset conditions 0 0 power on reset uu res reset during normal operation 01 res wake-up halt 1u wdt time-out during normal operation 1 1 wdt wake-up halt note:u means unchanged if crystal mask option is selected, the m c clock can be fed by x1, x2 decoder input clock (see application circuit 2). the functional units chip reset status is shown in the following table. pc 0000h interrupt disabled prescaler cleared wdt cleared. after master reset, wdt starts counting. programmable timer counter off timer/event counter off programmable tone generator off pager decoder off input/output ports input mode sp points to the top of the stack reset circuit reset configuration HT9480 17 23th feb 98
labels (tmrc0 and tmrc1) bits function 0~2 unused bits, read as 0 te 3 to define the tmr0 and tmr1 active edge of programmable timer counter and timer/event counter (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer counting (0=disabled; 1=enabled) - 5 unused bits, read as 0 tm0 tm1 6 7 to define the operation mode 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc register programmable timer counter and timer/event counter the programmable timer counter (tmr0) and timer/event counter (tmr1) are constructed us- ing the same structure. both counters contain an 8Cbit programmable count-up counter, whose clocks may come from an external source or from the system clock divided by 4. if the internal instruction clock is selected, only one reference time-base is provided. the exter- nal clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. the clock of the programmable timer counter should come from the external clock of the 75hz for real time clock (rtc) if a 76.8khz crystal is used. there are two sets of registers related to the programmable timer counter and to the timer/event counter namely, tmr0 (0dh) and tmrc0 (0eh) and tmr1 (10h) and tmrc1 (11h). there are also two physical registers mapped to the tmr0 and tmr1 locations: writing to tmr0 and tmr1 puts the starting value in the programmable timer counter and in the timer/event counter preload registers, while reading them gets the contents of the two counters. tmrc0 and tmrc1 are control reg- isters used to define some timer options. the tm0 and tm1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source may come from either a 256hz generator (for tmr0) or an external pin (for tmr1). the timer mode functions as a normal timer, with the clock source coming from the instruction clock or from the outputs of the tmr1 prescaler (tmr0 cannot be used in this mode). the pulse width measurement mode can be used to count the high or low level duration of the external signal tmr1, tmr0 is also disabled in this mode. the counting is based on the system clock. in the event count or timer mode, once the programmable timer counter or timer/event counter starts counting, it will count from the current contents in the counter to ffh. once an overflow occurs, the counter is reloaded from its counter preload register and generates an in- terrupt request flag (t0f; bit 5 of intc and t1f; bit 6 of intc for programmable timer counter and timer/event counter, respectively). on the other hand, in the pulse width measure- ment mode with the ton bit equal to one, when the tmr1 receives a transient from low to high (or high to low depending upon the te bit) it will start counting until the tmr1 returns to the original level and resets the ton as well. HT9480 18 23th feb 98
the states of the registers are summarized below. register power-on reset (por) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time- out (halt)* tmr0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrc0 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u-- tmr1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrc1 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u-- pc 0000h 0000h 0000h 0000h 0000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pcc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu note: * means warm reset u means unchanged x means unknown the measured result will remain in the timer/event counter even when the activated transient occurs again. in other words, only one cycle measurement can be made until the ton is set. the cycle measurement will re-function as long as further transient pulses are received. note that, in this operation mode, the timer/event counter starts counting not accord- ing to the logic level but to the transient edges. in the case of counting overflows, the counter is re-loaded from its counter preload register and issues an interrupt request, similar to the other two modes. to enable the counting operation, the value of the timer on bit (ton; bit 4 of tmrc0 and tmrc1) is 1. in the pulse width measurement mode, the ton is automatically cleared after the measurement cycle is completed. in the other two modes, namely the event count or timer mode, the ton can be reset only by in- structions. the overflow of the programmable timer counter and of the timer/event counter can be configured as one of the wake-up sources. no matter what type of operation mode is chosen, writing a 0 to et0i and et1i disables the interrupt service of the programmable timer counter and the timer/event counter, re- spectively. HT9480 19 23th feb 98
timer/event counter programmable tone generator in the case of the programmable timer counter and a timer/event counter off condition, writ- ing data to their preload registers also reloads that data to their counters. but if the program- mable timer counter or the timer/event counter is turned on, data written to the counter is kept only in its preload register, and the counter still goes on operating until an overflow occurs. after the counter (reading tmr0 or tmr1) is read, the clock is blocked to avoid errors. the programmer should take clock blocking into consideration, since this may result in timing counting errors. programmable tone generator the programmable tone generator is imple- mented in the HT9480. the programmable tone generator contains an 8-stage programmable frequency divider (mapping to the 1dh address of the m c), a 4-stage programmable frequency prescaler (set by spf10 and spf11), and a fre- quency source selector (set by spf17). when 1dh=00h, the tone generator is disabled and bz outputs high. but when 1dh is of any value greater than zero the generator is enabled. the value of the frequency divider, ranging from 2~256, is always greater than the assigned value by 1. the output of the 8-stage divider is divided by 2 to generate an output of (1/2 or 1/4) duty cycle on bz. the 4-stage programmable frequency prescaler is shown below. spf10 spf11 prescaler divider factor 00 1 01 2 10 4 11 8 the above setting of the prescaler divider factor is designed for applications on melodies or sound effects. the frequency source selector is set by spf17. when spf17=0, the value of the frequency source selector is the system clock. on the other hand, when spf17=1, the value of the selector turns out to be 32.768khz. for instance, if the HT9480 20 23th feb 98
input/output ports desired output of bz is 2.73khz, the frequency source is 32.768khz, the values of spf10 and spf11 are both set to 0, and the value of the programmable frequency divider is set to 5. input/output ports there are 7 input lines, and 10 input/output lines in the HT9480, which are labeled as pa, and pb; pc (pc0, pc1). these are mapped to [12h], and [14h]; [16h] of the data memory, respectively. port a is an input port only while port b and port c (pc0 and pc1) are bidirec- tional i/o ports. for input operation, the ports a, b, and c are non-latched, i.e., the inputs have to be ready at the t2 rising edge of the instruc- tion mov a, [m] (m=12h, 14h, 16h). for output operation, data is latched and then re- mains unchanged until the output latch is re- written. the pb and pc (pc0, pc1) i/o lines have their own control registers (pbc, pcc) to control the input/output configuration. these control regis- ters, tri-state (control register=1) or cmos (control register=0) with pull-high (option) structures can be reconfigured dynamically (i.e., on-the-fly) by software control. to function as an input, the corresponding i/o latch and related bit of the control register should be writ- ten 1 to avoid external logical violation. these control registers are mapped to location 15h, and 17h (bit 0 and bit 1 of 17h). after a chip reset, these input/output lines stay at high levels or floating (by mask option). they are defined as input types by writing 1 to the control registers and as output types by writing 0 to the control registers. each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=14h only) in- structions. some instructions first input data and then follow the output operations. for example, set [m].i, clr [m].i, cpl [m], cpla [m] read the entire port states into the cpu, exe- cute the defined operation (bit-operation), and then write the results back to the latches or the accumulator. each line of port a is capable of waking up the device (when a falling edge occurs) and is deter- mined by mask option. the highest four bits of port c are not physically implemented. reading them gets a 0, but writing them leads to no operation. bit 7 of port a connects a battery fall interrupt and a wake-up function. bit 7 of port a wakes up the m c each time a battery is changed. bit 2 of port c is used for internal subsystem oscilla- tor low-power function control (1: non-active; 0 : active). the value of bit 2 of port c is set as 1 at an initial power on. bit 3 of port c is used for lcd power control (1: lcd turn-on; 0 : lcd turn-off). the value of bit 3 of port c is also set as 1 at the initial power on. HT9480 21 23th feb 98
display memory lcd display the lcd display memory is embedded in the data memory (mapped to the addresses c0h~e2h of bank 27). it can be read and writ- ten to as a normal data memory. the following figure illustrates the mapping between the dis- play memory and the lcd pattern. to turn the display on/off, the programmer writes 1 or 0 to the corresponding bit of the display memory. the lcd display module can be of any form as long as the number of the common doesnt exceed 4 and the number of the segment is not over 35. the entire number of the lcd driver output is 35 4. the lcd driver can directly drive an lcd of 1/4 duty cycle and 1/3 bias. all of the lcd segments are random at the initial clear mode. the frequency of the lcd driving clock is fixed at about 256hz, and cannot be changed. it is set by holtek according to the application. the following is an example of an 8-segment digit display, which shows a waveform of 5. pager decoder the pager decoder is a pocsag code pager decoder at 512, 1200, or 2400 bps data rate, compatible with ccir radio paging code no.1 (pocsag code). the decoder supports six user addresses and six independently programma- ble user frames. HT9480 22 23th feb 98
the operation of the decoder is controlled by a pager control address (1eh) in conjunction with a pager data address (1fh). upon receipt of a valid call the data ready interrupt is generated. the pocsag paging code the ccir radio paging code no.1 (pocsag code) is constructed according to the follow- ing rules: a transmission consists of a preamble fol- lowed by a batch of complete code words. each batch begins with a synchronization codeword (sc). the format of the signal is illustrated in the following figure. each transmission begins with a preamble to achieve bit synchronization. the preamble is a pattern of one and zero; 10101010... re- peated for a period of at least 576 bits. codewords are transmitted in batches. each batch consists of a synchronization codeword followed by 8 frames. each frame consists of 2 codewords. the eight frames are numbered 0 through 7. all pagers are similarly divided into 8 groups. each pager is assigned to one of the 8 frames according to the 3 least signifi- cant bits (lsb) of its 21-bit identity code (ad- dress). the 3 bits are called receiver identity code (ric). pocsag code structure lcd timing HT9480 23 23th feb 98
a codeword is either an address or a message codeword. idle codewords are transmitted to fill in empty batches or to separate messages. an address codeword is coded as shown above. of the 21 bits of user addresses, 18 bits are coded in the codeword itself (bits 2 to 19), which is protected against transmission er- rors by a number of crc checkbits (bits 22 to 31). bit 32 is an overall even-parity bit. the two function bits (bits 20 and 21) allow distinction of four different calls to one user ad- dress as shown in following table. bit 20 (msb) bit 21 (lsb) call type data format 0 0 numeric 4-bits per digit 0 1 alert only 1 0 alert only 1 1 alpha-numeric 7-bits per ascii character an idle codeword is a valid address codeword, which cannot be allocated to the pager. there is a total of 20 bits of caller information to be put into a message codeword (bits 2 to 21), which is protected by the crc checkbits (bits 22 to 31). decoding of the pocsag data stream the pocsag coded input data received from rf module is first filtered by an internal digi- tal filter in the decoder. from the filtered data, a sampling clock synchronous to the data rate is derived. the decoder supports 512, 1200, and 2400 bits per second data rate, which in turn results in their corresponding sampling clock frequency. upon detection of a valid call, the decoder performs several operations (refer to the fol- lowing section of the message data transfer). call termination is normally deemed when a valid idle or another address codeword is re- ceived after a message code word. erroneous codewords upon receipt of erroneous uncorrectable code- words, call termination occurs according to the conditions given below: spf08 spf09 call termination event 0x any two consecutive codewords or the codeword directly following the address codeword in error 1 0 any single codeword in error 11 any two consecutive codewords in error error correction item description preamble 4 random errors in 31 bits synchronization code-word 2 random errors in 32 bits address code-word 2 random errors, or 4-bit burst errors (optional) message code-word 2 random errors, or 4-bit burst errors (optional) in the HT9480 error correction methods have been implemented as shown in above table. random error correction is default for both ad- dress and message code-words. burst error cor- rection can be switched by spf 15. up to 4 bits of burst errors can be corrected. decoder interface the HT9480 has two interfaces available. one is the pager control address (1eh), which con- trols the operation and configuration of the de- coder. the other is the pager data address (1fh), which places the message data of calls in the parallel mode. HT9480 24 23th feb 98
decoder control address the decoder control address (1eh) contains a data ready flag ( dr), a battery low flag ( bl), an out of range flag ( or), a battery fail flag ( bf), a decoder standby flag (stb), a call termination indication flag ( ct), a decoder software reset ( res), and a decoder on/off control bit ( on). it not only records the status information but controls the operation of the decoder. any data written to the decoder control ad- dress cannot change the or, bf, stb and ct flags. if the status of the battery fail ( bf) changes from 1 to 0, the following conditions occur. the pager controller generates an interrupt if the value of the data ready interrupt flag is 1. the pager controller does not generate an interrupt and no data is transmitted if the value of the data ready interrupt flag is 0. on the other hand, if the status of the battery fail ( bf) changes from 0 to 1, the internal node pa.7 of the pager controller will supply a wake-up function. after the decoder asserts the data transfer request, the data ready interrupt is generated and the dr bit (bit 7 of 1eh) is cleared low; then the data ready interrupt subroutine runs to process the call data and resets the dr bit high. decoder interface HT9480 25 23th feb 98
the function bits ( on, res) and indication bits ( ct, stb, bf, or, bl and dr) are all used to control the status of the decoder which is operated through the pager control address as described in the following table. pager data address the pager data address (1fh) are the parallel data lines for decoder data transfer. symbol bit r/w description on 0r/w on/off control bit this bit selects the on or standby state of the decoder. 0: on state 1: standby state res 1r/w reset output for the decoder core the m c has to set the res bit low and then high after the pager controller is turned on. ct 2 r call termination indication bit this bit decides the call termination status, when a valid code-word is received 0: end of code-word receive 1: receiving message code-word stb 3r standby indication bit when the value of the on bit is 1, the system goes into the standby state. the standby state allows the m c to execute the configuration ram setting. bf 4 r battery fail indication bit once the decoder detects that the battery fail interrupt is low, the bf bit will be low but unlatched. or 5 r out-of-range indication bit whenever the decoder detects an out-of-range condition, this bit is cleared low after end of the programmed out-of-range hold of time that is selected by the configuration registers (spf06 and spf07). the out-of-range indication may be tested for an out-of-range condition whenever the interface enable of the decoder is active; otherwise the or is normally high. the out-of-range indication is set high by detection of a valid data transmission or by switching the decoder to be in the standby state. bl 6r/w battery low indication bit the battery low indication is periodically tested for a battery low condition. if the decoder encounters a battery low condition the battery low indication bit is cleared low. at this time, the m c should set the bl bit high. dr 7 r/w data ready interrupt indication bit when a valid call is detected, data starts transfer. the dr bit becomes low when the serial data is changed to parallel data (1fh). after reading the parallel data, the m c software has to set the dr bit high. HT9480 26 23th feb 98
numeric message data transfer message data transfer the decoder outputs a deformatted address word and message words upon receipt of a valid call. the message data to be transferred is or- ganized into 8-bit words and transferred through the parallel pager data address (1fh) byte by byte. when a call word starts, the de- coder generates a data ready interrupt simulta- neously and runs the processing subroutine. the subroutine should read out the word in the pager data address (1fh) before the next call word comes in, i.e., the word should be read in 4ms at 512/1200 bit data rate and in 2ms at a 2400 bit data rate. otherwise, the data in 1fh is overridden by the next word. HT9480 27 23th feb 98
alpha-numeric message data transfer HT9480 28 23th feb 98
termination word format successful call termination occurs by the recep- tion of a valid address code-word with less than 2 bit errors on the decoder output register. unsuccessful termination occurs when sync is not detected. termination word format: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 error flag 0000100 call data output format the HT9480 automatically converts message code-words received in numeric or alphanu- meric format into ascii format. depending on spf09 and the function bit setting in the re- ceived address code-word a conversion takes place as shown in the following table. function bits message format spf 09 bit 20 bit 21 0 x x numeric 100numeric 1 x 1 alpha-numeric 1 1 x alpha-numeric when a conversion from alphanumeric format to ascii takes place, the received message code-words are split into message blocks, seven bits in length. after adding the error flag they are transferred as message words. when a conversion from numeric format to ascii takes place, the received message code-words are split into blocks, four bits in length. each four bit block is converted to a seven bit block as shown in the following table. after adding the error flag they are transferred as message words. refer to the numeric format to ascii conversion table. there is a new message packaging method after receipt of message code-words. the new mes- sage packaging method is 4 bits packaging type. depending upon spf20=1, message code-word conversion takes place as show in the following table. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 error flag 000d3d2d1d0 the received message code-words are split into blocks, four bits in length. each four bit block is directly transferred to a four bit block. after adding the error flag they are transferred as message words. HT9480 29 23th feb 98
numeric format to ascii conversion: 4-bit block character 7-bit block msb lsb msb lsb 0000 0 011000 0 0001 1 011000 1 0010 2 011001 0 0011 3 011001 1 0100 4 011010 0 0101 5 011010 1 0110 6 011011 0 0111 7 011011 1 1000 8 011100 0 1001 9 011100 1 1010 * 010101 0 1011 u 101010 1 1100 010000 0 1101 - 010110 1 1110 ] 101110 1 1111 [ 101101 1 synch word indication the synch word recognized by HT9480 is the standard pocsag synchronization code-word, as shown in the following table. bit no.0123456789101112131415 bit 0111110011010010 bit no. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit 0001010111011000 idle word indication the idle word recognized by the HT9480 is the standard pocsag idle code-word, as shown in the following table. bit no.0123456789101112131415 bit 0111101010001001 bit no. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit 1100000110010111 HT9480 30 23th feb 98
error indication after error correction, any code-word contain- ing more than two bits random error or four bits burst error (option) in address or message code- word may be indicated from the error flag posi- tion. data transfer data transfer is initiated once the code-word is already received. when the HT9480 is ready to transfer the received call data, an external in- terrupt will be generated via output int. any message data can be read by accessing the 1fh address of the m c ram map via the m c internal bus. the address word indicates call address, func- tion bit setting, and decoder flags. the message code-words are received and concatenated to a valid call address word. the message words derived from un-corrected message code-words. data transfer for a received call ends right after the termination word is transferred. address word format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sync. state call address dup. call 0 function code bit 0: bit 21 of the address code-word bit 1: bit 20 of the address code-word bit 2=0 is to tell the difference between termi- nation and address word format bit 3=1 if a duplicate code-word. bit 6 bit 5 bit 4 call address 000 ric a 001 ric b 010 ric c 011 ric d 100 ric e 101 ric f 110 111 bit 7= 1 if an address code-word is received in the data fail mode. interrupt indication the HT9480 provides an internal data ready interrupt and a battery fail interrupt. the in- ternal data ready interrupt and battery fail interrupt share the same pin connection. checking the battery fail interrupt bit ( bf; bit 4 of 1eh) and the data ready interrupt bit ( dr; bit 7 of 1 eh) will tell which type of interrupt has occurred. both interrupt bits are active low. out-of-range indication the out-of-range condition occurs when the time interval defined by spf06, spf07 does not receive any preamble or sync code word. this signal will be used as loss of rf signal indica- tor. HT9480 31 23th feb 98
address bit definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40h ena a00 a01 a02 a03 a04 a05 a06 41h a07 a08 a09 a10 a11 a12 a13 a14 42h a15 a16 a17 fa2 fa1 fa0 43h enb b00 b01 b02 b03 b04 b05 b06 44h b07 b08 b09 b10 b11 b12 b13 b14 45h b15 b16 b17 fb2 fb1 fb0 46h enc c00 c01 c02 c03 c04 c05 c06 47h c07 c08 c09 c10 c11 c12 c13 c14 48h c15 c16 c17 fc2 fc1 fc0 49h end d00 d01 d02 d03 d04 d05 d06 4ah d07 d08 d09 d10 d11 d12 d13 d14 4bh d15 d16 d17 fd2 fd1 fd0 4ch ene e00 e01 e02 e03 e04 e05 e05 4dh e07 e08 e09 e10 e11 e12 e13 e14 4eh e15 e16 e17 fe2 fe1 fe0 4fh enf f00 f01 f02 f03 f04 f05 f05 50h f07 f08 f09 f10 f11 f12 f13 f14 51h f15 f16 f17 ff2 ff1 ff0 52h spf00 spf01 spf02 spf03 spf04 spf05 spf06 spf07 53h spf08 spf09 spf10 spf11 spf12 spf13 spf14 spf15 54h spf16 spf17 spf18 spf19 spf20 spf21 spf22 spf23 duplicate call suppression the HT9480 provides a duplicate call suppres- sion with time-out facility, to identify duplicate call reception. in display pager mode, duplicate call indication is achieved only via the m c inter- face. a call is assumed to be duplicate if its address and function bit setting is equal to the latest received call, which initialized the call address and function bit reference. the dupli- cate call suppression time-out is selected by programming spf06, spf07. configuration ram organization the decoder contains a 21-byte ram to store 6 user addresses, 6 independently programmable frame numbers and specially programmed function bits (spf00~spf23) for the decoder application configuration. the data memory is mapped to the addresses 40h~54h of bank 27. HT9480 32 23th feb 98
user address format a user address in the pocsag code consists of 21 bits. three of the 21 bits are coded in the frame number and are therefore not explicitly transmitted. in the decoder, the addresses a, b, c, d, e and f can use 6 different frames respec- tively. every address has to be explicitly en- abled by resetting the associated enable bit. examples: address decimal value: rica=10535 binary equivalent(14 bits): 10100100100111 binary equivalent(18+3 bits): 000000010100100100111 register allocation: a00 a01 a02 a03 a04 a05 a06 a07 a08 000000010 a09 a10 a11 a12 a13 a14 a15 a16 a17 100100100 fr12 fr11 fr10 111 configuration the program mode changes to the standby state by setting the on bit high at any time. the configuration ram can be programmed only when the value of the stb flag is 1. after the configuration ram is programmed and the on bit is set low, the system quits the program mode and resumes normal operation. test mode the test mode of the decoder is selected by setting the ts pin low at any time. in the test mode, the rf control outputs bs1 and bs3 are set high constantly, but bs2 is set low. after the ts pin is set high the decoder exits the test mode. rf control the HT9480 provides the bs1-bs3 signals for rf control. bs1: receiver enabled receiver establishment time (t bs1 ) option 512 bps 1200/2400 bps spf00 spf01 7.81ms 53.33ms 0 0 15.63ms 6.67ms 0 1 31.25ms 13.33ms 1 0 62.50ms 26.67ms 1 1 bs2: quick charge rf dc level adjustment time (t bs2 ) option 512 bps 1200/2400 bps spf02 spf03 7.81ms 1.67ms 0 0 11.71ms 6.67ms 0 1 15.63ms 11.67ms 1 0 19.53ms 13.33ms 1 1 bs3: pll enabled pll establishment time (t bs3 ) option 512 bps 1200/2400 bps spf04 spf05 0ms 0ms 0 0 31.25ms 26.67ms 0 1 46.87ms 40.00ms 1 0 62.50ms 53.33ms 1 1 timing timing HT9480 33 23th feb 98
description of the special programmed function bits (spf) the following features can be selected by appro- priate programming of the specially pro- grammed function bits: spf00, spf01 receiver (bs1) establishment time (for the bs2~bs3 options, refer to spf2~spf5) 00: 7.81ms/512 53.33ms/1200/2400 01: 15.63ms/512 6.67ms/1200/2400 10: 31.25ms/512 13.33ms/1200/2400 11: 62.50ms/512 26.67ms/1200/2400 spf02, spf03 rf dc level adjustment (bs2) enable time 00: 7.81ms/512 1.67ms/1200/2400 01: 11.71ms/512 6.67ms/1200/2400 10: 15.63ms/512 11.67ms/1200/2400 11: 19.53ms/512 13.33ms/1200/2400 spf04, spf05 pll (bs3) establishment time 00: 0ms/512 0ms/1200/2400 01: 31.25ms/512 40.00ms/1200/2400 10: 46.87ms/512 40.00ms/1200/2400 11: 62.50ms/512 53.33ms/1200/2400 spf06, spf07 duplicate the call suppress time-out and out- of-range hold-off time-out 00: 30s/512/1200 15s/2400 01: 60s/512/1200 30s/2400 10: 120s/512/1200 60s/2400 11: 240s/512/1200 120s/2400 spf08, spf09 call termination criteria combination method and message data deformatting method 0x : any two consecutive codewords or the codeword directly following the address codeword in error 10 : any single codeword in error 11 : any two consecutive codewords in error x0 : numeric data deformation x1 : numeric data deformation on function code 00 only spf10, spf11 tone generation frequency prescaler divider 00: prescaler factor 1 01: prescaler factor 2 10: prescaler factor 4 11: prescaler factor 8 HT9480 34 23th feb 98
baud rate selection bits (spf12, spf13, spf14) spf12 spf13 spf14 connected crystal (hz) baud rate (hz) 0 0 0 32768 512 0 0 1 76.8k 512 0 1 0 76.8k 1200 0 1 1 76.8k 2400 1 0 0 153.6k 512 1 0 1 153.6k 1200 1 1 0 153.6k 2400 spf15 1: 4-bit burst error correction for address and message code-word 0: 2-bit random error correction for address and message code-word spf16 1: out-of-range hold-off period according to spf06 and spf07 0: out-of-range hold-off period is zero regardless of spf06 and spf07 spf17 tone generation frequency source selector 0: system clock 1: 32.768khz spf18 tone generation frequency duty control 0: frequency duty cycle 1/2 1: frequency duty cycle 1/4 spf19 non-inversion or inversion data input selection 1: inversion input selected for di from rf circuit, referring to di 0: non-inversion input selected for di from rf circuit spf20 message code-word packaging method 1: 4 bits packaging mode 0: 7 bits ascii mode spf21, spf22, spf23 internal state status (for testing only) HT9480 35 23th feb 98
mask option the following table illustrates nine kinds of mask options in the HT9480. all of the options should be defined to ensure proper system functioning. no. mask option 1 halt function selection. this option defines the way of enabling or disabling the halt function. 2 wdt source selection. this option selects the wdt source, from either the subsystem clock, or instruction clock, or disabling the wdt function. 3 clrwdt times selection. this option defines the way of clearing the wdt by instruction. once means that the clr wdt can clear the wdt and twice implies that the clr wdt1 and clr wdt2 should be executed before the time-out so as to clear the wdt. 4 wake-up selection. this option defines the wake-up activity. port a has the capability of waking-up the chip from halt. 5 pb, pc0, and pc1 pull-high options 6 m c osc type selection. this option is to decide if an rc or crystal oscillator is chosen as the system clock. 7 wdt prescaler selection. the prescaler can be set to 1/1024 or 1/2048 8 fout connection selection. the fout output can be connected to the osc1 input or not. 9 double frequency selection. the fout can be doubled from the x1 input clock. HT9480 36 23th feb 98
application circuit 1 HT9480 37 23th feb 98
application circuit 2 HT9480 38 23th feb 98
instruction set summary mnemonic description flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to register with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry with result in data memory decimal adjust acc for addition with result in data memory z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry none none c c none none c c HT9480 39 23th feb 98
mnemonic description flag affected data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditional skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter powerdown mode none none none to,pd to*,pd* to*,pd* none none to,pd notes: x= 8-bit immediate data ? = flag(s) is affected m= 8-bit data memory address C= flag(s) is not affected a= accumulator *= flag(s) may be affected by the result of the execution i= 0...7 number of bits addr= 13-bit program memory address HT9480 40 23th feb 98
instruction definition adc a,[m] add data memory and carry to accumulator description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. operation acc ? acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? adcm a,[m] add accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. operation [m] ? acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? add a,[m] add data memory to accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc ? acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? add a,x add immediate data to accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc ? acc+x affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? HT9480 41 23th feb 98
addm a,[m] add accumulator to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] ? acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory performs a bitwise logical_and operation. the result is stored in the accumulator. operation acc ? acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC and a,x logical and immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logi- cal_and operation. the result is stored in the accumulator. operation acc ? acc and x affected flag(s) tc2 tc1 to pd ov z ac c C CCCC ? CC andm a,[m] logical and data memory with accumulator description data in the specified data memory and the accumulator performs a bitwise logical_and operation. the result is stored in the data memory. operation [m] ? acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c C CCCC ? CC HT9480 42 23th feb 98
call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this ad- dress. operation stack ? pc+1 pc ? addr affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC clr [m] clear data memory description the contents of the specified data memory are cleared to zero. operation [m] ? 00h affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to zero. operation [m].i ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC clr wdt clear watchdog timer description the wdt and the wdt prescaler are cleared (re-counting from zero). the powerdown bit (pd) and time-out bit (to) are cleared. operation wdt and wdt prescaler ? 00h pd and to ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C C00CCCC HT9480 43 23th feb 98
clr wdt1 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. only execu- tion of this instruction without the other preclear instruction sets the indi- cating flag which implies this instruction was executed. the pd and to flags remain unchanged. operation wdt and wdt prescaler ? 00h* pd and to ? 0* affected flag(s) tc2 tc1 to pd ov z ac c C C0*0*CCCC clr wdt2 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. only execu- tion of this instruction without the other preclear instruction, sets the indicating flag which implies this instruction was executed. the pd and to flags remain unchanged. operation wdt and wdt prescaler ? 00h* pd and to ? 0* affected flag(s) tc2 tc1 to pd ov z ac c C C0*0*CCCC cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1s comple- ment). bits which previously contain a one are changed to zero and vice- versa. operation [m] ? [ m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT9480 44 23th feb 98
cpla [m] complement data memory - place result in accumulator description each bit of the specified data memory is logically complemented (1s comple- ment). bits which previously contained a one are changed to zero and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remains unchanged. operation acc ? [ m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary code decimal) code. the accumulator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be created if the low nibble of the accumulator is greater than 9. the bcd adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if (acc.3~acc.0) >9 or ac=1 then ([m].3~[m].0) ? (acc.3~acc.0)+6, ac1= ac else ([m].3~[m].0) ? (acc.3~acc.0), ac1=0 if (acc.7~acc.4)+ac1 >9 or c=1 then ([m].7~[m].4) ? (acc.7~acc.4)+6+ac1, c=1 else ([m].7~[m].4) ? (acc.7~acc.4)+ac1, c=c affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCC ? dec [m] decrement data memory description data in the specified data memory is decremented by one operation [m] ? [m]C1 affected flag(s) tc2 tc1 to pd ov z ac c C CCCC ? CC HT9480 45 23th feb 98
deca [m] decrement data memory - place result in accumulator description data in the specified data memory is decremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc ? [m]C1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC halt enter powerdown mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc ? pc+1 pd ? 1 to ? 0 affected flag(s) tc2 tc1 to pd ov z ac c C C01CCCC inc [m] increment data memory description data in the specified data memory is incremented by one operation [m] ? [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC inca [m] increment data memory - place result in accumulator description data in the specified data memory is incremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc ? [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT9480 46 23th feb 98
jmp addr direct jump description bits 0~11 of the program counter are replaced with the directlyCspecified address unconditionally, and control passed to this destination. operation pc ? addr affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC mov a,[m] move data memory to accumulator description the contents of the specified data memory is copied to the accumulator. operation acc ? [m] affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC mov a,x move immediate data to accumulator description the 8Cbit data specified by the code is loaded into the accumulator. operation acc ? x affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC mov [m],a move accumulator to data memory description the contents of the accumulator is copied to the specified data memory (one of the data memories). operation [m] ? acc affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC nop no operation description no operation is performed. execution continues with the next instruction. operation pc ? pc+1 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 47 23th feb 98
or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memory) performs a bitwise logical_or operation. the result is stored in the accumulator. operation acc ? acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC or a,x logical or immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logical_or operation. the result is stored in the accumulator. operation acc ? acc or x affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC orm a,[m] logical or data memory with accumulator description data in the data memory (one of the data memory) and the accumulator performs a bitwise logical_or operation. the result is stored in the data memory. operation [m] ? acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC ret return from subroutine description the program counter is restored from the stack. this is a two-cycle instruc- tion. operation pc ? stack affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 48 23th feb 98
ret a,x return and place immediate data in accumulator description the program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. operation pc ? stack acc ? x affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC reti return from interrupt description the program counter is restored from the stack, and interrupts enabled by setting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). operation pc ? stack emi ? 1 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC rl [m] rotate data memory left description the contents of the specified data memory is rotated left one bit with bit 7 rotated into bit 0. operation [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0-6) [m].0 ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC rla [m] rotate data memory left-place result in accumulator description data in the specified data memory is rotated left one bit with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0-6) acc.0 ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 49 23th feb 98
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are together rotated left one bit. bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) ? [m].i; [m].i:bit i of the data memory (i=0-6) [m].0 ? c c ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCC ? rlca [m] rotate left through carry-place result in accumulator description data in the specified data memory and the carry flag are together rotated left one bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) ? [m].i; [m].i:bit i of the data memory (i=0-6) acc.0 ? c c ? [m].7 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCC ? rr [m] rotate data memory right description the contents of the specified data memory are rotated right one bit with bit 0 rotated to bit 7. operation [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0-6) [m].7 ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 50 23th feb 98
rra [m] rotate right - place result in accumulator description data in the specified data memory is rotated right one bit with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) ? [m].(i+1); [m].i:bit i of the data memory (i=0-6) acc.7 ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated right one bit. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i ? [m].(i+1); [m].i:bit i of the data memory (i=0-6) [m].7 ? c c ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCC ? rrca [m] rotate right through carry - place result in accumulator description data of the specified data memory and the carry flag are together rotated right one bit. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i ? [m].(i+1); [m].i:bit i of the data memory (i=0-6) acc.7 ? c c ? [m].0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCC ? HT9480 51 23th feb 98
sbc a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the accumulator. operation acc ? acc+[ m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? sbcm a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the data memory. operation [m] ? acc+[ m]+c affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? sdz [m] skip if decrement data memory is zero description the contents of the specified data memory are decremented by one. if the result is zero, the next instruction is skipped. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaced to get the proper instruction. this makes a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]C1)=0, [m] ? ([m]C1) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 52 23th feb 98
sdza [m] decrement data memory-place result in acc, skip if zero description the contents of the specified data memory are decremented by one. if the result is zero, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction, that makes a 2 cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]C1)=0, acc ? ([m]C1) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC set [m] set data memory description each bit of the specified data memory is set to one operation [m] ? ffh affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC set [m].i set bit of data memory description bit i of the specified data memory is set to one operation [m].i ? 1 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC siz [m] skip if increment data memory is zero description the contents of the specified data memory is incremented by one. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, [m] ? ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 53 23th feb 98
siza [m] increment data memory-place result in acc, skip if zero description the contents of the specified data memory is incremented by one. if the result is zero, the next instruction is skipped and the result stored in the accumu- lator. the data memory remains unchanged. if the result is zero, the follow- ing instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, acc ? ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC snz [m].i skip if bit i of the data memory is not zero description if bit i of the specified data memory is not zero, the next instruction is skipped. if bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m].i 1 0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC sub a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the accumulator. operation acc ? acc+[ m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? subm a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula- tor, leaving the result in the data memory. operation [m] ? acc [ m]+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? HT9480 54 23th feb 98
sub a,x subtract immediate data from accumulator description the immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc ? acc+ x+1 affected flag(s) tc2 tc1 to pd ov z ac c CCCC ???? swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. operation [m].3~[m].0 ? [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC swapa [m] swap data memory-place result in accumulator encryption the low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 ? [m].7~[m].4 acc.7~acc.4 ? [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC sz [m] skip if data memory is zero description if the contents of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 55 23th feb 98
sza [m] move data memory to acc, skip if zero description the contents of the specified data memory is copied to accumulator. if the contents is zero, the following instruction, fetched during the current instruc- tion execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m]=0, acc ? [m] affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC sz [m].i skip if bit i of the data memory is zero description if bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a 2-cycle instruction. otherwise proceed with the next instruction. operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC tabrdc [m] move rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] ? rom code (low byte) tblh ? rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC tabrdl [m] move rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] ? rom code (low byte) tblh ? rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c C CCCCCCC HT9480 56 23th feb 98
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory performs a bitwise logical exclusive_or operation and the result is stored in the accumulator. operation acc ? acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC xorm a,[m] logical xor data memory with accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclusive_or operation. the result is stored in the data memory. the zero flag is affected. operation [m] ? acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC xor a,x logical xor immediate data to accumulator description data in the the accumulator and the specified data perform a bitwise logical exclusive_or operation. the result is stored in the accumulator. the zero flag is affected. operation acc ? acc xor x affected flag(s) tc2 tc1 to pd ov z ac c CCCCC ? CC HT9480 57 23th feb 98

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